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31407 ms pc 20060915-s00004 no.a0584-1/14 specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. LV5254LG overview the LV5254LG is an inverting charge pump regulator ic. functions ? inverting charge pump regulator specifications absolute maximum ratings at ta = 25 c, sgnd and pgnd = 0v parameter symbol conditions ratings unit input supply voltage v dd max sv dd = pv dd 6.5 v vs pin input voltage vs max 6.5 v stby pin input voltage stby max 6.5 v s1 and s2 pin input voltage s1, s2 max 6.5 v maximum output current i out 110 ma operating temperature topr -20 to +85 c storage temperature tstg -40 to +125 c recommended operating conditions at ta = 25 c, sgnd and pgnd = 0v parameter symbol conditions ratings unit input supply voltage v dd sv dd = pv dd 3.5 to 6 v vs pin input voltage vs 1 to 4.5 v output current i out 100 ma bi-cmos lsi inverting charge pump regulator ic orderin g numbe r : ena0584
LV5254LG no.a0584-2/14 electrical characteristics (a) electrical characteristics ta = 25c, sv dd and pv dd = 4.6v, sgnd and pgnd = 0v, clk = 2mhz, unless otherwise specified. ratings parameter symbol conditions min typ max unit output ripple vrp c2, c5 = 1 f, i o = 60ma 20 mvp-p standby mode v dd current i dd stby 1 a operating v dd current 1 i dd ope1 i o = 0ma 2.2 ma operating v dd current 2 i dd ope2 i o = 60ma 3.2 ma power efficiency peff v dd = 4.6v, v out = -2.8v, i out = 60ma 57.5 % reference voltage v ref 1.262 1.300 1.339 v overcurrent protection threshold current i ocp 115 ma overcurrent protection latch off wait time t ocp fclk = 2mhz 6 ms regulator output on time tregon fclk = 2mhz 3.5 ms internal clock frequency* fclk 2 mhz thermal shutdown circuit operating temperature tsd design guarantee 170 c v out discharge resistance rdis 650 vs pin input resistance rvs 180 280 480 k stby pin pull-down resistance rshd 100 170 300 k v th h 1.6 v dd v stby pin control voltage v th l 0 0.3 v v th h 0.7v dd v dd v s1 and s2 pin control voltage v th l 0 0.3 v * : the charge pump operating frequency, fcp, is the internal clock frequency divided by two, i.e. fclk/2. (b) output characteristics ta = 25c, sv dd and pv dd = 4.6v, sgnd and pgnd = 0v, clk = 2mhz, unless otherwise specified. fixed output voltage (vout = -2.8v) mode outputs a fixed voltage of -2.8v determined by an internal resistor. ratings parameter symbol conditions min typ max unit input supply voltage v dd sv dd = pv dd 4.37 4.83 v output voltage precision v out v dd = +4.37 to +4.83v i out = 60ma -2.884 -2.8 -2.716 v maximum output current i out v dd = +4.37 to +4.83v v out = -2.8v 70 ma vs mode outputs a voltage that is -1 times the voltage vs input to the vs pin. ratings parameter symbol conditions min typ max unit vs pin input voltage vs 1 4.5 v vs pin output voltage range v out *1 -4.5 -1 v output voltage precision vs = 1 to 2v, i out = 0 to 60ma -1.05vs -vs -0.95vs v output voltage precision vs = 2 to 4.5v, i out = 0 to 60ma -1.03vs -vs -0.97vs v
LV5254LG no.a0584-3/14 external setting mode outputs a voltage determined by external resistors and the external reference voltage. see page 8, external setting mode applications and the output voltage setting method for the method for setting the v out voltage. ratings parameter symbol conditions min typ max unit output voltage range v out *1 -4.5 -1 v fb pin voltage vfb v dd = 5v, i out = 0 to 100ma -5 20 mv fb pin current ifb v dd = 5v, i out = 0 to 100ma 70 200 na *1 : the v out range that can be set and the current drive capacity of the char ge pump regulator are, in principle, determined by the relatio nship between the values of the v dd voltage and the set voltage. (see the "relationship between the i nput and output voltages" ) contact your sanyo semiconductors representative for more detailed information. logic function tables the pins s1 and s2 must be connected to v dd (high) or ground (low) according to the mode to be used. mode description s1 s2 mode 1 outputs a fixed voltage of -2.8v determined by an internal resistor. high low mode 2 outputs a voltage that is -1 times the voltage vs input to the vs pin. low high mode 3 outputs a voltage determined by an external resistor and the external reference voltage. high high package dimensions unit : mm (typ) 3330 3.0 3.0 13 245 0.5 0.5 0.5 0.5 0.8 0.0nom 0.05 0.3 ed cba top view side view bottom view sanyo : flga24(3.0x3.0) ambient temperature, ta ? c allowable power dissipation, pd max ? mw pd max ? ta 0 0.6 0.7 0.4 0.2 0.8 ? 20 60 80 40 20 010 0 specified board : 50 40 0.8mm 3 glass epoxy 4-layer (2s2p) printed circuit board
LV5254LG no.a0584-4/14 pin assignment flga24 (3mm 3mm) pin descriptions pin no. pin functions 9 sv dd small signal system v dd 11 pv dd power system v dd 1 sgnd small signal system ground 15 pgnd power system ground 13 c1 + inversion capacitor connection (driver side) 17 c1 - inversion capacitor connection (charge transfer side) 18 c2 charge pump output 21 v out regulator output 24 vref band gap voltage output 22 fb feedback pin 23 vs vs mode output setting 2 stby standby mode control 4 s1 sensing mode selection 1 3 s2 sensing mode selection 2 8 test test mode enable (normally not used) * : the test mode enable pin must be left open. (there is a bui lt-in pull-down resistor, and this pin should always be low.) edcba 1 2 3 4 5 vref sgnd s2 s1 stby fb vs pgnd c1 + c2 c1 - 1 3 2 4 5 7 6 12 13 15 17 18 22 23 24 v out test sv dd pv dd 20 14 10 8 11 9 16 19 21 top view
LV5254LG no.a0584-5/14 block diagram and application circuit example 1 (internal fixed-voltage mode) ? use ceramic capacitors for the external capacitors and connect them as close as possible to the ic. we recommend using class b devices with excellent temperature characteristics.) ? use capacitors with the same values fo r the charge pump capacitors c1 and c2. we recommend a capacitance of 1 f for c1 and c2. (see figure 4 on page 10) ? sv dd and pv dd must be at the same potential. short them togeth er with the shortest possi ble line and use a ceramic capacitor with a value of 1 f or greater for c4 (which is inserted between this point and pgnd). c4 must be mounted as close as possible to the ic. ? c6 is a phase compensation capacitor. it is required for stable regulator operation. vref c1 + c1 - v out c2 = 1 f fb stby pgnd on off c1 = 1 f c5 = 1 f osc pv dd v dd c4 = 10 f vref c3 = 0.1 f vs + ? s1 s2 sgnd sv dd test c6 v out charge pump clock driver output tr error amplifier overcurrent protection thermal shutdown discharge c2 v dd
LV5254LG no.a0584-6/14 application circuit example 2 (vs mode) application circuit example 3 (external setting mode) vref c1 + c1 - v out c2 = 1 f fb stby pgnd on off c1 = 1 f c5 = 1 f osc pv dd v dd c4 = 10 f vref c3 = 0.1 f vs vs + ? s1 s2 sgnd sv dd test c6 v out c2 v dd charge pump clock driver output tr error amplifier overcurrent protection thermal shutdown discharge vref c1 + c1 - v out c2 = 1 f fb r2 r1 stby pgnd on off c1 = 1 f osc pv dd v dd c4 = 10 f vref c3 = 0.1 f vs + ? s1 s2 sgnd sv dd test c2 v dd c5 = 1 f c6 v out vref_ext charge pump clock driver output tr error amplifier overcurrent protection thermal shutdown discharge
LV5254LG no.a0584-7/14 recommended power on and off sequences (1) apply the v dd voltage to the sv dd and pv dd pins. (2) if vs mode is used, apply the vs voltage. if external setting mode is used, apply the external reference voltage. (3) start pre-charging the flying capacitor w ith a high-level input to the stby pin. (4) start charging the pump-up capacitor with the charge pump sub-driver (soft start). (5) switch to the charge pump driver. this starts charging of the pump-up capacitor by the main driver. (6) regulator output starts. (7) stop ic drive by applying a low-level input to the stby pin to start v out output discharge operation by the internal discharge transistor. (this operates when the stby pin is low.) (8) if vs mode is used, shut down the vs voltage, and if exte rnal setting mode is used, shut down the external reference voltage. (9) shut down the v dd voltage. sv dd (pin 9) pv dd (pin 11) v dd -v dd v out stby (pin 2) cp clk (1mhz) cp output c2 (pin 18) regulator output v out (pin 21) vs (pin 23) : vs mode or vref_ext (external reference voltage) external setting mode tpre : 0.5ms tsoft : 2ms tregon : 3.5ms ton : 1ms (1) (2) (3) (4) (5) (6) (7) (8) (9)
LV5254LG no.a0584-8/14 overcurrent protection operation this ic includes a function that protects against overcurrent in v out . if the v out output is shorted and a large current flows, the ic will latch and stop the output. to reco ver from this stopped state, set the stby pin low and then set it high again. external setting mode applications and the output voltage setting method in the lv5254's external setting mode, the output voltage is set by the external resistors r1 and r2 and by the external reference voltage, vref_ext. in this mode, the output voltage is expressed by equation (1). the second term in equation (1) is the error amplifier's offset component and the third term is the offset component due to the feedback current. the voltage precision achieved by an application can be determin ed by considering the tolerances of the parameters in equation (1). v out = - r 2 r 1 ? vref_ext+ r 1+ r 2 r 1 ? vfb-r 2 ? ifb (1) fb c5 c6 r2 r1 v out vref_ext v out ifb vfb
LV5254LG no.a0584-9/14 relationship between the input and output voltages equation (2) gives the relationship between the input voltage and output voltage. in the lv5254, a charge pump circuit generates vc2, which is the v in level inverted, and generates the output voltage v out by regulating that inverted voltage. in this case, due to the charge pump block impedance ron, the voltage drop i o ron (where i o is the load current) is generated. (* here we are ignoring the capacitor loss components in the charge pump capacitors c1 and c2.) the lv5254's current ca pacity is expressed by equation (3). at th is time, the impedance ron increases with temperature. thus the current capacity de creases with increasing temperature. v out = vc2+ vreg = (-v in +ron i out )+ vreg (2) v out : output voltage, v in : input voltage, i out : load current, ron : charge pump block impedance, vreg : regulator voltage drop i o [max] = (v in +v out - vreg [min]) / ron (3) i o [max] : maximum load current, vreg [min] : minimum regulator voltage drop figure 1 : charge pump block impedance temperature ch aracteristics : assumed worst case (c1, c2 = 1 f) ambient temperature, ta ? c cp on-resistance, ron ? ron ? ta 12 16 17 18 15 14 13 19 ? 20 60 80 40 20 090 v dd = 5v cp ron i out vreg voltage drop due to the charge pump block impedance input voltage v in cp output voltage vc2 regulator output v out voltage drop in the regulator block regulator i out load current iou t
LV5254LG no.a0584-10/14 next, consider figure 2, which shows the relationship between the input voltage v in and the charge pump block impedance ron at ta = 85c, which is the maximum temperat ure for which operation is gu aranteed. at ta = 85c, if vreg [min] = 0.3v (inferred worst case value), the lv5254's maximum output current can be expressed as equation (4). i o [max] = (v in +v out -0.3) / ron (4) the current capacity shown in figure 3 can be determined from the characteristics in figure 2 when v out is set to be -3v. caution : the characteristics values presented in this reference documentation are nothing other than inferred worst-case values. no guarantee or warranty is made with respect to these values. loss in the charge pump capacitors voltage loss occurs in the pump capacito rs c1 and c2 in the charge pump circuit. figure 4 shows the charge pump output vs. load current characteristics (with the c1 and c2 value as a parameter) at room temperature when v dd = 5v. note that the load regulation becomes wo rse as the value of the capacitors c1 and c2 is reduced. to minimize the loss in these capacitor, we recommend using a value of 1 f for c1 and c2. figure 4 : charge pump output - load current characteristics when v dd = 5v, data provided for reference purposes. input voltage, v in ?v figure 2 figure 3 cp on-resistance, ron ? ron ? v in 15 23 21 19 17 25 3.5 5.5 5 4.5 46 input voltage, v in ?v maximum output current, i o max ? m i o max ? v in 0 80 100 60 40 20 120 3.5 5 4.5 4 5.2 ta = 85c ta = 85c load current, i o ?ma charge pump output, vc2 ? v charge pump output ? load current characteristic s ? 5 ? 4.8 ? 4.6 ? 4.4 ? 4.2 ? 4 ? 3.8 ? 3.6 080 60 40 20 10 0 c1, c2 = 0.22 f c1, c2 = 0.47 f c1, c2 = 1 f figure 2 : charge pump block impedance - input voltage characteristics (ta = 85c) : assumed worst case ( c1 , c2 = 1 f)
LV5254LG no.a0584-11/14 ic start and stop 1. startup waveform (external setting mode) (a) no load - startup waveform (b) 50 - startup waveform 2. falling waveform (external setting mode) (a) no load - falling waveform (b) 50 - falling waveform internal fixed mode - regulator load regulation - internal fixed mode v dd = 4.6v ? 2.9 ? 2.875 ? 2.85 ? 2.825 ? 2.8 ? 2.775 ? 2.75 ? 2.725 ? 2.7 060 50 20 30 40 10 70 load current, i out ?ma output voltage, v out ?v ta = -20 c ta = 90 c efficiency - internal fixed mode v dd = 4.6v 0 10 20 30 40 50 60 70 060 50 20 30 40 10 70 load current, i out ?ma output voltage, v out ?v v dd = 4.6v ta = 90 c ta = -20 c room temperature room temperature 1 2 1.6v -2.9v 4msec -5v 3,4 stby vref c2 cp output v out 1 2 3,4 stby vref c2 cp outpu t v ou t 1ms/s ta = 27 c v dd = 5v i out = 0ma ta = 27 c v dd = 5v i out = 60ma 1.6v -2.9v -4.4v 4msec 1ms/s stby 2.00v/s 1 vref 1.00v/s 2 v out 2.00v/s 3 c2 2.00v/s 4 stby 2.00v/s 1 vref 1.00v/s 2 v out 2.00v/s 3 c2 2.00v/s 4 1 2 0v 0v -2.9v 3msec -5v 3,4 c2 cp output 1 2 3,4 c2 cp outpu t 1ms/s ta = 27 c v dd = 5v i out = 0ma ta = 27 c v dd = 5v i out = 60ma 3msec -2.9v -4.4v 1ms/s stby 2.00v/s 1 vref 1.00v/s 2 v out 2.00v/s 3 c2 2.00v/s 4 stby 2.00v/s 1 vref 1.00v/s 2 v out 2.00v/s 3 c2 2.00v/s 4 stby vref v out stby vref v ou t
LV5254LG no.a0584-12/14 vs mode - regulator vs mode (vs = 1v) load regulation v dd = 5v ? 1.1 ? 1.05 ? 1 ? 0.95 ? 0.9 06080 20 40 60 80 20 40 100 load current, i out ?ma output voltage, v out ?v vs mode (vs = 3.3v) load regulation v dd = 5v ? 3.4 ? 3.35 ? 3.3 ? 3.25 ? 3.2 060 20 40 80 load current, i out ?ma output voltage, v out ?v vs mode (vs = 2.5v) line regulation characteristics i out = 60ma ? 2.55 ? 2.525 ? 2.5 ? 2.475 ? 2.45 4.5 5 5.5 6 intput voltage, v dd ?v output voltage, v out ?v vs mode (vs = 1v) line regulation characteristics i out = 60ma ? 1.05 ? 1.025 ? 1 ? 0.975 ? 0.95 3.5 4 5 4.5 5.5 6 intput voltage, v dd ?v output voltage, v out ?v vs mode (vs = 4.5v) load regulation v dd = 6v ? 4.6 ? 4.55 ? 4.5 ? 4.45 ? 4.4 060 20 40 80 load current, i out ?ma output voltage, v out ?v vs mode (vs = 2.5v) load regulation v dd = 5v ? 2.6 ? 2.4 ? 2.45 ? 2.5 ? 2.55 0 100 load current, i out ?ma output voltage, v out ?v ta = 0 c ta = 30 c ta = 60 c ta = 90 c ta = -30 c ta = 0 c ta = 60 c ta = 30 c ta = 90 c ta = -30 c ta = 0 c ta = -30 c ta = 90 c ta = 90 c ta = 30 c ta = 0 c ta = 60 c ta = 30 c ta = -30 c ta = 60 c ta = 90 c ta = -30 c ta = room temperature ta = -30 c ta = 90 c ta = room temperature
LV5254LG no.a0584-13/14 external setting mode applications and the output voltage setting method overcurrent protection function detection current value load regulation characteristics ? 2.95 ? 2.94 ? 2.93 ? 2.92 ? 2.91 ? 2.89 ? 2.9 ? 2.88 060708090 20 30 10 40 50 5.5 5 100 load current, i out ?ma output voltage, v out ?v overcurrent protection - ambient temperature dependence characteristics 100 110 120 130 140 150 160 170 180 ? 40 ? 20 60 80 040 20 100 ambient temperature, ta ? c overcurrent protection function detection current value , ilim ? ma line regulation characteristics ? 2.95 ? 2.88 ? 2.9 ? 2.89 ? 2.93 ? 2.92 ? 2.91 ? 2.94 4.5 6 intput voltage, v dd ?v output voltage, v out ?v ta = 30 c ta = 0 c ta = -30 c ta = 90 c ta = 90 c ta = 0 c ta = 30 c ta = 60 c ta = 60 c v dd = 5v r1 = 82k r2 = 240k vref_ext = 1v i out = 60ma v dd = 5v r1 = 82k r2 = 240k vref_ext = 1v ta = -30 c v dd = 6v v dd = 5v v dd = 4v v dd = 5.5v v dd = 4.5v v dd = 3.5v
LV5254LG ps no.a0584-14/14 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of march, 2007. specifications and information herein are subject to change without notice.

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